MC68HC16Z1CAG16 Datasheet, PDF (426/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
D.6.15 Transmit Data RAM
TR[0:F] — Transmit Data RAM
$YFFD20 – $YFFD3F
Data that is to be transmitted by the QSPI is stored in this segment. The CPU16 nor-
mally writes one word of data into this segment for each queue command to be exe-
cuted. Information to be transmitted must be written to the transmit data RAM in a
right-justified format. The QSPI cannot modify information in the transmit data RAM.
The QSPI copies the information to its data serializer for transmission. Information re-
mains in the transmit RAM until overwritten.
D.6.16 Command RAM
CR[0:F] — Command RAM
$YFFD40 – $YFFD4F
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0¹
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
COMMAND CONTROL
PERIPHERAL CHIP SELECT
NOTES:
1. The PCS0 bit represents the dual-function PCS0/SS.
PCS0¹
Command RAM is used by the QSPI when in master mode. The CPU16 writes one
byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from
the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete. This allows
for transfers greater than 16 bits to peripherals without negation of their chip-
selects.
BITSE — Bits per Transfer Enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
D-52
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL