MC68HC16Z1CAG16 Datasheet, PDF (157/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
The mode configuration drivers are conditioned with R/W and DS to prevent conflicts
between external devices and the MCU when reset is asserted. If external RESET is
asserted during an external write cycle, R/W conditioning (as shown in Figure 5-18)
prevents corruption of the data during the write. Similarly, DS conditions the mode
configuration drivers so that external reads are not corrupted when RESET is asserted
during an external read cycle.
Alternate methods can be used for driving data bus pins low during reset. Figure 5-19
shows two of these options. The simplest is to connect a resistor in series with a diode
from the data bus pin to the RESET line. A bipolar transistor can be used for the same
purpose, but an additional current limiting resistor must be connected between the
base of the transistor and the RESET pin. If a MOSFET is substituted for the bipolar
transistor, only the 1 kΩ isolation resistor is required. These simpler circuits do not of-
fer the protection from potential memory corruption during RESET assertion as does
the circuit shown in Figure 5-18.
DATA PIN
1 kΩ
1N4148
DATA PIN
1 kΩ
2 kΩ
RESET
2N3906
RESET
ALTERNATE DATA BUS CONDITION CIRCUIT
Figure 5-19 Alternate Circuit for Data Bus Mode Select Conditioning
Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC-
TERISTICS. Do not confuse pin function with pin electrical state. Refer to 5.7.5 Pin
State During Reset for more information.
Unlike other chip-select signals, the boot ROM chip-select (CSBOOT) is active at the
release of RESET. During reset exception processing, the MCU fetches initialization
vectors beginning at address $000000 in supervisor program space. An external
memory device containing vectors located at these addresses can be enabled by
CSBOOT after a reset.
The logic level of DATA0 during reset selects boot ROM port size for dynamic bus al-
location. When DATA0 is held low, port size is eight bits; when DATA0 is held high,
either by the weak internal pull-up driver or by an external pull-up, port size is 16 bits.
Refer to 5.9.4 Chip-Select Reset Operation for more information.
DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively.
DATA[7:3] determine the functions of an associated chip-select and all lower-num-
bered chip-selects down through CS6. For example, if DATA5 is pulled low during
reset, CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain
chip-selects. Refer to 5.9.4 Chip-Select Reset Operation for more information.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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