MC68HC16Z1CAG16 Datasheet, PDF (113/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
C3
0.1 µF
C4
0.01 µF
V_SS
C1
0.1 µF
XFC¹
V_DDSYN
NORMAL OPERATING ENVIRONMENT
C3
0.1 µF
C1
R1
0.1 µF 18 kΩ
XFC^{1, 2}
C4
0.01 µF
V_SS
C2
0.01 µF
V_DDSYN
HIGH-STABILITY OPERATING ENVIRONMENT
1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE.
NORMAL/HIGH-STABILITY XFC CONN
Figure 5-5 System Clock Filter Networks
The synthesizer locks when the VCO frequency is equal to f_ref. Lock time is affected
by the filter time constant and by the amount of difference between the two comparator
inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta-
tus is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come
out of reset until the synthesizer locks. Crystal type, characteristic frequency, and lay-
out of external oscillator circuitry affect lock time.
When the clock synthesizer is used, SYNCR determines the system clock frequency
and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. When the W or
Y values change, VCO frequency changes, and there is a VCO relock delay. The SYN-
CR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When
X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency
is one-fourth the VCO frequency (f_VCO). When X = 1, a divide-by-two circuit is enabled
and system clock frequency is one-half the VCO frequency (f_VCO). There is no relock
delay when clock speed is changed by the X bit.
When a slow reference is used, one W bit and six Y bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. The X bit is lo-
cated in the VCO clock output path to enable dividing the system clock frequency by
two without disturbing the PLL.
When using a slow reference, the clock frequency is determined by SYNCR bit set-
tings as follows:
f_sys = 4f_ref(Y + 1)(2^{(2W + X)})
The reset state of SYNCR ($3F00) results in a power-on f_sys of 8.388 MHz when f_ref
is 32.768 kHz.
M68HC16 Z SERIES
SYSTEM INTEGRATION MODULE
USER’S MANUAL
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5-7
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