MC68HC16Z1CAG16 Datasheet, PDF (234/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
9.4.1 SCI Registers
The SCI programming model includes the QSM global and pin control registers, and
four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one sta-
tus register (SCSR), and one data register (SCDR). Refer to D.6 Queued Serial Mod-
ule for register bit and field definitions.
9.4.1.1 Control Registers
SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is
enabled. This register can be read or written.
SCCR1 contains a number of SCI configuration parameters, including transmitter and
receiver enable bits, interrupt enable bits, and operating mode enable bits. This regis-
ter can be read or written at any time. The SCI can modify the RWU bit under certain
circumstances.
Changing the value of SCI control bits during a transfer may disrupt operation. Before
changing register values, allow the SCI to complete the current transfer, then disable
the receiver and transmitter.
9.4.1.2 Status Register
SCSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCI hardware or by reading SCSR, then reading or writing SCDR. A long-word
read can consecutively access both SCSR and SCDR. This action clears receiver sta-
tus flag bits that were set at the time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after reading the asserted status
bits, but before reading or writing SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set, and SCDR must be read or written before the sta-
tus bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit al-
ready set in either byte is cleared on a subsequent read or write of SCDR.
9.4.1.3 Data Register
SCDR contains two data registers at the same address. The receive data register
(RDR) is a read-only register that contains data received by the SCI. Data enters the
receive serial shifter and is transferred to RDR. The transmit data register (TDR) is a
write-only register that contains data to be transmitted. Data is first written to TDR,
then transferred to the transmit serial shifter, where additional format bits are added
before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when
SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/
T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured
for 8-bit operation, they have no meaning or effect.
9-24
QUEUED SERIAL MODULE
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M68HC16 Z SERIES
USER’S MANUAL