MC68HC16Z1CAG16 Datasheet, PDF (484/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
pins 8-3
-to-digital converter (ADC). See ADC 8-1
Arbitration 9-3
AS 4-41, 5-31, 5-40, 5-43, 5-45, 5-47, 5-54
ASPC 7-2, 7-3, D-26
Asserted (definition) 2-6
Asynchronous exceptions 4-39
Autocorrelation 4-45
Autovector enable (AVEC). See AVEC 5-24
Auxiliary timer clock input (PCLK) 11-8
AVEC 5-24, 5-33, 5-43, 5-54, 5-60, 5-65, 5-67, 5-68, D-21
–B–
Background
debug mode 4-40, 4-42, 5-41
commands 4-43
connector pinout 4-45
enabling 4-42
entering 4-42
recommended connection 4-45
serial
I/O block diagram 4-44
interface 4-44
sources 4-42
timing
16.78 MHz A-37
20.97 MHz A-38
25.17 MHz A-38
freeze assertion A-39
low voltage, 16.78 MHz A-37
serial communication A-39
Basic operand size 5-35
Baud
clock 9-26, 10-18
rate generator 9-2
BCD 4-6
BERR 5-33, 5-37, 5-41, 5-43, 5-44, 5-45, 5-54, 5-60
BG 5-46, 5-49, 5-54, 5-65
BGACK 5-46, 5-49, 5-54, 5-65
Binary
coded decimal (BCD) 4-6
-weighted capacitors 8-5
BITS D-47
encoding field 9-18
Bits per transfer
enable (BITSE) D-52
field (BITS) D-47
BITSE 9-20, D-52
Bit-time 9-25, 10-17
BKPT 4-41, 5-41, 5-49, 5-52, 5-53, 5-57
Block size (BLKSZ) 5-65, D-18
encoding 5-65, D-18
BME 5-25, D-13
BMT 5-24, D-13
BOOT D-26
Boot ROM control (BOOT) 7-3, D-26
Bootstrap words (ROMBS) 7-1
BR 5-46, 5-49, 5-54, 5-64, 5-65
Break frame 9-25, 10-17
Breakpoint
acknowledge cycle 5-41
exceptions 4-40
hardware breakpoints 5-41
mode selection 5-52
operation 5-42
Breakpoints 4-41
Buffer amplifier 8-5
Built-in emulation memory C-1
Bus
arbitration
for a single device 5-46
timing — active A-33
timing — idle A-34
cycle
regular 5-37
terminations for asynchronous cycles 5-44
error
exception processing 5-44
signal (BERR). See BERR. 5-24
timing of 5-44
exception control cycles 5-43
grant (BG). See BG 5-46
grant acknowledge (BGACK). See BGACK 5-46
monitor 5-24
external enable (BME) D-13
timeout period 5-25
timing (BMT) 5-24, D-13
request (BR). See BR 5-46
state analyzer 4-40
BYTE (upper/lower byte option) 5-66, D-19
–C–
C 4-4, D-3
Capture/compare unit 11-1
block diagram 11-11
clock output enable (CPROUT) bit D-73
Carry flag (C) 4-4, D-3
Case outlines
132-pin package B-4
144-pin package B-7
CCF D-36
CCR 4-4, D-3
CCTR D-36
CD/CA D-33
C_DAC 8-22
Central processing unit (CPU16). See CPU16 4-1
C_F 8-22
CFORC 11-8, 11-13, 11-14, D-74
Channel selection for A/D conversion D-33
Charge sharing 8-23
Chip-select
base address registers (CSBAR) 5-64, 5-65
reset values 5-69
operation 5-67
option registers (CSOR) 5-64, 5-66, D-18
reset values 5-69
pin assignment registers (CSPAR) 5-63, D-17
field encoding 5-64
M68HC16 Z SERIES
I-2
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