MC68HC16Z1CAG16 Datasheet, PDF (327/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table A-26 25.17-MHz ECLK Bus Timing
(V_DD and V_DDSYN = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol Min
Max
E1 ECLK Low to Address Valid²
t_EAD
—
40
E2 ECLK Low to Address Hold
t_EAH
10
—
E3 ECLK Low to CS Valid (CS Delay)
t_ECSD
—
100
E4 ECLK Low to CS Hold
t_ECSH
10
—
E5 CS Negated Width
t_ECSN
20
—
E6 Read Data Setup Time
t_EDSR
25
—
E7 Read Data Hold Time
t_EDHR
5
—
E8 ECLK Low to Data High Impedance
t_EDHZ
—
40
E9 CS Negated to Data Hold (Read)
t_ECDH
0
—
E10 CS Negated to Data High Impedance
t_ECDZ
—
1
E11 ECLK Low to Data Valid (Write)
t_EDDW
—
2
E12 ECLK Low to Data Hold (Write)
t_EDHW
5
—
E13 CS Negated to Data Hold (Write)
E14 Address Access Time (Read)³
E15 Chip-Select Access Time (Read)⁴
t_ECHW
0
—
t_EACC
255
—
t_EACS
195
—
E16 Address Setup Time
t_EAS
—
1/2
NOTES:
1. All AC timing is shown with respect to V_IH/V_IL levels unless otherwise noted.
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t_Ecyc – t_EAD – t_EDSR.
4. Chip select access time = t_Ecyc – t_ECSD – t_EDSR.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
t_cyc
M68HC16 Z SERIES
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
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