MC68HC16Z1CAG16 Datasheet, PDF (148/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
BREAKPOINT OPERATION FLOW
CPU16
ACKNOWLEDGE BREAKPOINT
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET ADDR1 TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
NEGATE AS or DS
PERIPHERAL
ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING
NEGATE DSACK or BERR
INITIATE HARDWARE BREAKPOINT PROCESSING
CPU16 BREAKPOINT OPERATION FLOW
Figure 5-15 Breakpoint Operation Flowchart
5.6.4.2 LPSTOP Broadcast Cycle
Low-power stop mode is initiated by the CPU16. Individual modules can be stopped
by setting the STOP bits in each module configuration register. The SIM can turn off
system clocks after execution of the LPSTOP instruction. When the CPU16 executes
LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power mode when either an interrupt of higher priority than the interrupt mask lev-
el in the CPU16 condition code register or a reset occurs. Refer to 5.3.4 Low-Power
Operation and SECTION 4 CENTRAL PROCESSOR UNIT for more information.
During an LPSTOP broadcast cycle, the CPU16 performs a CPU space write to ad-
dress $3FFFE. This write puts a copy of the interrupt mask value in the clock control
logic. The mask is encoded on the data bus as shown in Figure 5-16.
The LPSTOP CPU space cycle is shown externally (if the bus is available) as an indi-
cation to external devices that the MCU is going into low-power stop mode. The SIM
provides an internally generated DSACK response to this cycle. The timing of this bus
cycle is the same as for a fast termination write cycle. If the bus is not available (arbi-
trated away), the LPSTOP broadcast cycle is not shown externally.
NOTE
BERR during the LPSTOP broadcast cycle is ignored.
5-42
SYSTEM INTEGRATION MODULE
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M68HC16 Z SERIES
USER’S MANUAL