MC68HC16Z1CAG16 Datasheet, PDF (244/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Select a value for INTV so that each MCCI interrupt vector corresponds to one of the
user-defined vectors ($40–$FF). Refer to the CPU16 Reference Manual (CPU16RM/
AD) for additional information on interrupt vectors.
10.2.2 Pin Control and General-Purpose I/O
The eight pins used by the SPI and SCI subsystems have alternate functions as gen-
eral-purpose I/O pins. Configuring the MCCI submodule includes programming each
pin for either general-purpose I/O or its serial interface function. In either function,
each pin must also be programmed as input or output.
The MCCI data direction register (MDDR) assigns each MCCI pin as either input or
output. The MCCI pin assignment register (MPAR) assigns the MOSI, MISO, and SS
pins as either SPI pins or general-purpose I/O. (The fourth pin, SCK, is automatically
assigned to the SPI whenever the SPI is enabled, for example, when the SPE bit in
the SPI control register is set.) The receiver enable (RE) and transmitter enable (TE)
bits in the SCI control registers (SCCR0A, SCCR0B) automatically assign the associ-
ated pin as an SCI pin when set or general-purpose I/O when cleared. Table 10-2
summarizes how pin function and direction are assigned.
Table 10-2 Pin Assignments
Pin
TXDA/PMC7
RXDA/PMC6
TXDB/PMC5
RXDB/PMC4
SS/PMC3
SCK/PMC2
MOSI/PMC1
MISO/PMC0
Function Assigned By
TE bit in SCCR0A
RE bit in SCCR0A
TE bit in SCCR0B
RE bit in SCCR0B
SS bit in MPAR
SPE bit in SPCR
MOSI bit in MPAR
MISO bit in MPAR
Direction Assigned By
MMDR7
MMDR6
MMDR5
MMDR4
MMDR3
MMDR2
MMDR1
MMDR0
10.3 Serial Peripheral Interface (SPI)
The SPI submodule communicates with external peripherals and other MCUs via a
synchronous serial bus. The SPI is fully compatible with the serial peripheral interface
systems found on othe Freescale devices, such as the M68HC11 and M68HC05 fam-
ilies. The SPI can perform full duplex three-wire or half duplex two-wire transfers. Se-
rial transfer of eight or sixteen bits can begin with the MSB or LSB. The system can be
configured as a master or slave device.
Figure 10-2 shows a block diagram of the SPI.
10-4
MULTICHANNEL COMMUNICATION INTERFACE
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M68HC16 Z SERIES
USER’S MANUAL