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MC68HC16Z1CAG16 Datasheet, PDF (308/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual
Freescale Semiconductor, Inc.
Table A-17 20.97-MHz AC Timing (Continued)
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1
Num
30
30A
31
33
35
37
39
39A
46
46A
47A
Characteristic
CLKOUT Low to Data In Invalid (Fast Cycle Hold)7
CLKOUT Low to Data In High Impedance7
DSACK[1:0] Asserted to Data In Valid9
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted10
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Symbol Min
tCLDI
10
tCLDH
—
tDADI
—
tCLBAN
—
tBRAGA
1
tGAGN
1
tGH
2
tGA
1
tRWA
115
tRWAS
70
tAIST
5
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR, HALT Asserted11
tAIHT
12
tDABA
—
53 Data Out Hold from Clock High
tDOCH
0
54 Clock High to Data Out High Impedance
tCHDH
—
55 R/W Asserted to Data Bus Impedance Change
tRADC
32
70 Clock Low to Data Bus Driven (Show Cycle)
tSCLDD
0
71 Data Setup Time to Clock Low (Show Cycle)
tSCLDS
10
72 Data Hold from Clock Low (Show Cycle)
tSCLDH
10
73 BKPT Input Setup Time
tBKST
10
74 BKPT Input Hold Time
tBKHT
10
75 Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins
tMSS
20
76 Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins
tMSH
0
77 RESET Assertion Time12
tRSTA
4
78 RESET Rise Time13
tRSTR
—
100 CLKOUT High to Phase 1 Asserted14
tCHP1A
3
101 CLKOUT High to Phase 2 Asserted14
tCHP2A
3
102 Phase 1 Valid to AS or DS Asserted14
tP1VSA
10
103 Phase 2 Valid to AS or DS Asserted14
tP2VSN
10
104 AS or DS Valid to Phase 1 Negated14
tSAP1N
10
105 AS or DS Negated to Phase 2 Negated14
tSNP2N
10
NOTES:
1. Refer to notes in Table A-18.
Max
—
72
46
23
—
2
—
—
—
—
—
—
30
—
23
—
23
—
—
—
—
—
—
—
10
40
40
—
—
—
—
Unit
ns
ns
ns
ns
tcyc
tcyc
tcyc
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcyc
ns
tcyc
tcyc
ns
ns
ns
ns
ns
ns
A-24
ELECTRICAL CHARACTERISTICS
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M68HC16 Z SERIES
USER’S MANUAL