MC68HC16Z1CAG16 Datasheet, PDF (406/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
PRS[4:0]
%00000
%00001
%00010
%00011
…
%11101
%11110
%11111
Table D-27 Prescaler Output
ADC Clock
Reserved
System Clock/4
System Clock/6
System Clock/8
…
System Clock/60
System Clock/62
System Clock/64
Minimum
System Clock
—
2.0 MHz
3.0 MHz
4.0 MHz
…
30.0 MHz
31.0 MHz
32.0 MHz
Maximum
System Clock
—
8.4 MHz
12.6 MHz
16.8 MHz
…
—
—
—
D.5.5 ADC Control Register 1
ADCTL1 — ADC Control Register 1
15
RESET:
NOT USED
$YFF70C
7
6
5
4
3
2
1
0
SCAN MULT S8CM CD CC CB CA
0
0
0
0
0
0
0
ADCTL1 is used to initiate an A/D conversion and to select conversion modes and a
conversion channel or channels. It can be read or written at any time. A write to
ADCTL1 initiates a conversion sequence. If a conversion sequence is already in
progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC
status register.
SCAN — Scan Mode Selection
0 = Single conversion
1 = Continuous conversions
Length of conversion sequence(s) is determined by S8CM.
MULT — Multichannel Conversion
0 = Conversion sequence(s) run on a single channel selected by [CD:CA].
1 = Sequential conversions of four or eight channels selected by [CD:CA].
Length of conversion sequence(s) is determined by S8CM.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
This bit determines the number of conversions in a conversion sequence. Table D-28
displays the different ADC conversion modes.
D-32
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
M68HC16 Z SERIES
USER’S MANUAL