MC68HC16Z1CAG16 Datasheet, PDF (127/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
5.3.3 External Bus Clock
The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E-
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devic-
es and peripherals. ECLK frequency can be set to system clock frequency divided by
eight or system clock frequency divided by sixteen. The clock is enabled by the
CS10PA[1:0] field in chip-select pin assignment register 1 (CSPAR1). ECLK operation
during low-power stop is described in the following paragraph. Refer to 5.9 Chip-Se-
lects for more information about the external bus clock.
5.3.4 Low-Power Operation
Low-power operation is initiated by the CPU16. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To mini-
mize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SIM brings the MCU out of
low-power stop mode when one of the following exceptions occur:
• RESET
• Trace
• SIM interrupt of higher priority than the stored interrupt mask
Refer to 5.6.4.2 LPSTOP Broadcast Cycle for more information.
During a low-power stop mode, unless the system clock signal is supplied by an ex-
ternal source and that source is removed, the SIM clock control logic and the SIM clock
signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for
the RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to gen-
erate the CLKOUT signal while in low-power stop mode.
During low-power stop mode, the address bus continues to drive the LPSTOP instruc-
tion, and bus control signals are negated. I/O pins configured as outputs continue to
hold their previous state; I/O pins configured as inputs will be in a high-impedance
state.
STSIM and STEXT bits in SYNCR determine clock operation during low-power stop
mode.
The flowchart shown in Figure 5-6 summarizes the effects of the STSIM and STEXT
bits when MC68HC16Z1, MC68CK16Z1, MC68CM16Z1, MC68HC16Z2, and
MC68HC16Z3 MCUs enter normal low-power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on. Figure 5-7 summarizes the effects
of the STSIM and STEXT bits when MC68HC16Z4 and MC68CK16Z4 MCUs enter
normal low-power stop mode.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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