MC68HC16Z1CAG16 Datasheet, PDF (443/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Name
—
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
TO
PAOV
PAI
Table D-43 GPT Interrupt Sources
Source Number
Source
0000
Adjusted Channel
0001
Input Capture 1
0010
Input Capture 2
0011
Input Capture 3
0100
Output Compare 1
0101
Output Compare 2
0110
Output Compare 3
0111
Output Compare 4
1000
Input Capture 4/Output Compare 5
1001
Timer Overflow
1010
Pulse Accumulator Overflow
1011
Pulse Accumulator Input
Vector Number
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
IPL[2:0] — Interrupt Priority Level
This field specifies the priority level of interrupts generated by the GPT.
IVBA[3:0] — Interrupt Vector Base Address
Most significant nibble of interrupt vector numbers generated by the GPT. Refer to Ta-
ble D-43.
D.8.4 Port GP Data Direction Register/Data Register
DDRGP/PORTGP — Port GP Data Direction Register/Data Register
15
14
13
12
11
10
9
8
7
6
5
4
3
DDGP[7:0]
PORTGP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
$YFF906
2
1
0
0
0
0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input
or output and PORTGP holds the 8-bit data.
DDGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
D.8.5 OC1 Action Mask Register/Data Register
OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register
$YFF908
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OC1M[5:1]
0
0
0
OC1D[5:1]
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that
determines which pins are affected. OC1D determines what the outputs are.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
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