MC68HC16Z1CAG16 Datasheet, PDF (191/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table 8-2 Multiplexer Channel Sources
[CD:CA] Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Input Source
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Reserved
Reserved
Reserved
Reserved
V_RH
V_RL
(V_RH – V_RL) / 2
Test/Reserved
8.6.2 Sample Capacitor and Buffer Amplifier
Each of the eight external input channels is associated with a sample capacitor and
share a single sample buffer amplifier. After a conversion is initiated, the multiplexer
output is connected to the sample capacitor at the input of the sample buffer amplifier
for the first two ADC clock cycles of the sampling period. The sample amplifier buffers
the input channel from the relatively large capacitance of the RC DAC array.
During the second two clock cycles of a sampling period, the sample capacitor is dis-
connected from the multiplexer, and the sample buffer amplifier charges the RC DAC
array with the value stored in the sample capacitor.
During the third portion of a sampling period, both sample capacitor and buffer ampli-
fier are bypassed, and multiplexer input charges the DAC array directly. The length of
this third portion of a sampling period is determined by the value of the STS field in
ADCTL0.
8.6.3 RC DAC Array
The RC DAC array consists of binary-weighted capacitors and a resistor-divider chain.
The array performs two functions: it acts as a sample hold circuit during conversion,
and it provides each successive digital-to-analog comparison voltage to the compara-
tor. Conversion begins with MSB comparison and ends with LSB comparison. Array
switching is controlled by the digital subsystem.
M68HC16 Z SERIES
ANALOG-TO-DIGITAL CONVERTER
USER’S MANUAL
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