MC68HC16Z1CAG16 Datasheet, PDF (154/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

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5.7 Reset
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when
RESET is asserted, reset does not occur until the clock starts. Resets are clocked to
allow completion of write cycles in progress at the time RESET is asserted.
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The SIM de-
termines whether a reset is valid, asserts control signals, performs basic system con-
figuration and boot ROM selection based on hardware mode-select inputs, then
passes control to the CPU16.
5.7.1 Reset Exception Processing
The CPU16 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the ex-
ception vector table. The exception vector table consists of 256 four-byte vectors and
occupies 512 bytes of address space. The exception vector table can be relocated in
memory by changing its base address in the vector base register (VBR). The CPU16
uses vector numbers to calculate displacement into the table. Refer to 4.13 Excep-
tions for more information.
Reset is the highest-priority CPU16 exception. Unlike all other exceptions, a reset oc-
curs at the end of a bus cycle, and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset excep-
tion, and cannot be restarted. Only essential reset tasks are performed during excep-
tion processing. Other initialization tasks must be accomplished by the exception
handler routine. Refer to 5.7.9 Reset Processing Summary for details on exception
processing.
5.7.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes request signals
to CLKOUT, and asserts reset control signals. Reset control logic can drive three dif-
ferent internal signals.
• EXTRST (external reset) drives the external reset pin.
• CLKRST (clock reset) resets the clock module.
• MSTRST (master reset) goes to all other internal circuits.
All resets are gated by CLKOUT. Asynchronous resets are assumed to be catastroph-
ic. An asynchronous reset can occur on any clock edge. Synchronous resets are timed
to occur at the end of bus cycles. The SIM bus monitor is automatically enabled for
synchronous resets. When a bus cycle does not terminate normally, the bus monitor
terminates it. Table 5-18 is a summary of reset sources.
5-48
SYSTEM INTEGRATION MODULE
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M68HC16 Z SERIES
USER’S MANUAL