MC68HC16Z1CAG16 Datasheet, PDF (266/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
IC1/PGP0
IC2/PGP1
IC3/PGP2
CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
PRESCALER
PWM UNIT
BUS INTERFACE
OC1/PGP3
OC2/OC1/PGP4
OC3/OC1/PGP5
OC4/OC1/PGP6
IC4/OC5/OC1/PGP7
PAI
PCLK
PWMA
PWMB
IMB
Figure 11-1 GPT Block Diagram
GPT BLOCK
11.2 GPT Registers and Address Map
The GPT programming model consists of a configuration register (GPTMCR), parallel
I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,
TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL),
pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,
PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,
TMSK2). Functions of the module configuration register are discussed in 11.3 Special
Modes of Operation and 11.4 Polled and Interrupt-Driven Operation. Other regis-
ter functions are discussed in the appropriate sections.
All registers can be accessed using byte or word operations. Certain capture/compare
registers and pulse-width modulation registers must be accessed by word operations
to ensure coherency. If byte accesses are used to read a register such as the timer
counter register (TCNT), there is a possibility that data in the byte not being accessed
will change while the other byte is read. Both bytes must be accessed at the same
time.
The modmap (MM) bit in the system integration module configuration register
(SIMCR) defines the most significant bit (ADDR23) of the IMB address for each regis-
ter in the MCU. Because the CPU16 drives ADDR[23:20] to the same logic state as
ADDR[19:0], MM must equal one.
11-2
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M68HC16 Z SERIES
USER’S MANUAL