MC68HC16Z1CAG16 Datasheet, PDF (321/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table A-19 Low Voltage 16.78-MHz Background Debug Mode Timing
(V_DD and V_DDSYN = 2.7 to 3.6Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
B6 CLKOUT High to FREEZE Asserted/Negated
B7 CLKOUT High to IPIPE1 High Impedance
B8 CLKOUT High to IPIPE1 Valid
B9 DSCLK Low Time
t_DSISU
t_DSIH
t_DSCSU
t_DSCH
t_DSOD
t_DSCCYC
t_FRZAN
t_IFZ
t_IF
t_DSCLO
B10 IPIPE1 High Impedance to FREEZE Asserted
t_IPFA
B11 FREEZE Negated to IPIPE[0:1] Active
t_FRIP
NOTES:
1. All AC timing is shown with respect to V_IH/V_IL levels unless otherwise noted.
Min
15
15
15
15
—
2
—
—
—
1
TBD
TBD
Max
—
—
—
—
35
—
50
50
50
—
—
—
Unit
ns
ns
ns
ns
ns
t_cyc
ns
ns
ns
t_cyc
t_cyc
t_cyc
Table A-20 16.78-MHz Background Debug Mode Timing
(V_DD and V_DDSYN = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Characteristic
Symbol
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
B6 CLKOUT High to FREEZE Asserted/Negated
B7 CLKOUT High to IPIPE1 High Impedance
B8 CLKOUT High to IPIPE1 Valid
B9 DSCLK Low Time
B10 IPIPE1 High Impedance to FREEZE Asserted
B11 FREEZE Negated to IPIPE[0:1] Active
t_DSISU
t_DSIH
t_DSCSU
t_DSCH
t_DSOD
t_DSCCYC
t_FRZAN
t_IFZ
t_IF
t_DSCLO
t_IPFA
t_FRIP
NOTES:
1. All AC timing is shown with respect to V_IH/V_IL levels unless otherwise noted.
Min
15
10
15
10
—
2
—
—
—
1
TBD
TBD
Max
—
—
—
—
25
—
50
TBD
TBD
—
—
—
Unit
ns
ns
ns
ns
ns
t_cyc
ns
ns
ns
t_cyc
t_cyc
t_cyc
M68HC16 Z SERIES
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
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