MC68HC16Z1CAG16 Datasheet, PDF (375/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
APPENDIX D
REGISTER SUMMARY
This appendix contains address maps, register diagrams, and bit/field definitions for
M68HC16 Z-series MCUs. More detailed information about register function is provid-
ed in the appropriate sections of the manual.
Except for central processing unit resources, information is presented in the intermod-
ule bus address order shown in Table D-1.
Table D-1 Module Address Map
Module
SIM
SRAM
MRM
(MC68HC16Z2/MC68HC16Z3 only)
ADC
QSM
MCCI
(MC68HC16Z4, MC68CK16Z4 only)
GPT
Size
(Bytes)
128
8
32
64
512
64
64
Base
Address
$YFFA00
$YFFB00
$YFF820
$YFF700
$YFFC00
$YFFC00
$YFF900
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in the SIM module configuration reg-
ister (SIMCR) determines where the control registers block is located in the system
memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF;
when MM = 1, register addresses range from $FFF000 to $FFFFFF.
With the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless driven exter-
nally. MM corresponds to IMB ADDR23. If it is cleared, the SIM maps IMB modules
into address space $7FF000 – $7FFFFF, which is inaccessible to the CPU16. Mod-
ules remain inaccessible until reset occurs. The reset state of MM is one, but the bit is
can be written once. Initialization software should make certain it remains set.
D.1 Central Processing Unit
CPU16 registers are not part of the module address map. Figure D-1 is a functional
representation of CPU resources.
M68HC16 Z SERIES
REGISTER SUMMARY
USER’S MANUAL
For More Information On This Product,
D-1
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