MC68HC16Z1CAG16 Datasheet, PDF (293/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table A-10 25.17-MHz Clock Control Timing
(V_DD and V_DDSYN = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H)
Num
Characteristic
PLL Reference Frequency Range¹
1
MC68HC16Z1
MC68HC16Z2
MC68HC16Z3
System Frequency²
On-Chip PLL System Frequency
2
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
External Clock Operation
PLL Lock Time^{1, 7, 8, 9}
Changing W or Y in SYNCR or exiting from
3
LPSTOP³
Warm Start-Up⁴
Cold Start-Up (fast reference option only)⁵
4 VCO Frequency⁶
Limp Mode Clock Frequency
5 SYNCR X bit = 0
SYNCR X bit = 1
CLKOUT Jitter^{1, 7, 8, 9, 10}
6
Short term (5 µs interval)
Long term (500 µs interval)
Symbol
f_ref
f_sys
t_lpll
f_VCO
f_limp
J
clk
Min
20
3.2
3.2
dc
4 (f_ref)
4 (f_ref) /128
dc
Max
50
5.2
5.2
25.17
25.17
25.17
25.17
—
—
—
—
—
—
–1.0
–0.05
20
50
75
2 (f_sys max)
f_sys max/2
f_sys max
1.0
0.5
Unit
kHz
MHz
MHz
MHz
ms
MHz
MHz
%
NOTES:
1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires
a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the
MC68HC16Z3 requires a 4.194 MHz crystal reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that V_DDSYN and V_DD are stable, that an external filter is attached to the XFC pin, and that the crystal
oscillator is stable.
4. Assumes that V_DDSYN is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator
is stable, followed by V_DD ramp-up. Lock time is measured from V_DD at specified minimum to RESET negated.
5. Cold start is measured from V_DDSYN and V_DD at specified minimum to RESET negated.
6. Internal VCO frequency (f_VCO) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-
vide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f_sys = f_VCO ÷ 4.
When X = 1, the divider is disabled, and f_sys = f_VCO ÷ 2.
X must equal one when operating at maximum specified f_sys.
7. This parameter is periodically sampled rather than 100% tested.
8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 MΩ to guarantee this
specification. Filter network geometry can vary depending upon operating environment.
9. Proper layout procedures must be followed to achieve specifications.
10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-
mum f_sys. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-
nal clock signal. Noise injected into the PLL circuitry via V_DDSYN and V_SS and variation in crystal oscillator
frequency increase the J_clk percentage for a given interval. When jitter is a critical constraint on control system
operation, this parameter should be measured during functional testing of the final system.
M68HC16 Z SERIES
ELECTRICAL CHARACTERISTICS
USER’S MANUAL
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