MC68HC16Z1CAG16 Datasheet, PDF (145/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
MCU
ADDRESS DEVICE (S0)
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
ASSERT AS (S1)
PLACE DATA ON DATA[15:0] (S2)
ASSERT DS AND WAIT FOR DSACK (S3)
OPTIONAL STATE (S4)
NO CHANGE
PERIPHERAL
ACCEPT DATA (S2 + S3)
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
TERMINATE OUTPUT TRANSFER (S5)
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
START NEXT CYCLE
TERMINATE CYCLE
NEGATE DSACK
Figure 5-13 Write Cycle Flowchart
WR CYC FLOW
5.6.3 Fast Termination Cycles
When an external device can meet fast access timing, an internal chip-select circuit
fast termination option can provide a two-cycle external bus transfer. Because the
chip-select circuits are driven from the system clock, the bus cycle termination is in-
herently synchronized with the system clock.
If multiple chip-selects are to be used to provide control signals to a single device and
match conditions occur simultaneously, all MODE, STRB, and associated DSACK
fields must be programmed to the same value. This prevents a conflict on the internal
bus when the wait states are loaded into the DSACK counter shared by all chip-se-
lects.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
For More Information On This Product,
Go to: www.freescale.com
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