MC68HC16Z1CAG16 Datasheet, PDF (330/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table A-28 QSPI Timing
(V_DD and V_DDSYN = 5.0 Vdc ± 5% for 16.78 MHz, 10% for 20/25 MHz, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Function
Symbol
Min
Max
Operating Frequency
1 Master
Slave
f_op
DC
1/4
DC
1/4
Cycle Time
2 Master
Slave
t_qcyc
4
510
4
—
Enable Lead Time
3 Master
Slave
t_lead
2
128
2
—
Enable Lag Time
4 Master
Slave
t_lag
—
1/2
2
—
Clock (SCK) High or Low Time
5 Master
Slave²
Sequential Transfer Delay
6 Master
Slave (Does Not Require Deselect)
t_sw
2 t_cyc – 60 255 t_cyc
2 t_cyc – n
—
t_td
17
8192
13
—
Data Setup Time (Inputs)
7 Master
Slave
t_su
30
—
20
—
Data Hold Time (Inputs)
8 Master
Slave
t_hi
0
—
20
—
9 Slave Access Time
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
11 Master
Slave
t_a
—
1
t_dis
—
2
t_v
—
50
—
50
Data Hold Time (Outputs)
12 Master
Slave
t_ho
0
—
0
—
Rise Time
13 Input
Output
t_ri
—
2
t_ro
—
30
Fall Time
14 Input
Output
t_fi
—
2
t_fo
—
30
NOTES:
1. All AC timing is shown with respect to V_IH/V_IL levels unless otherwise noted.
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
Unit
f_sys
f_sys
t_cyc
t_cyc
t_cyc
t_cyc
SCK
t_cyc
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
µs
ns
µs
ns
A-46
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
M68HC16 Z SERIES
USER’S MANUAL