MC68HC16Z1CAG16 Datasheet, PDF (75/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
Table 4-2 Instruction Set Summary (Continued)
Mnemonic
Operation
ASRA
Arithmetic Shift Right
A
Description
Address
Mode
INH
Instruction
Condition Codes
Opcode Operand Cycles S MV H EV N Z V C
370D
—
2
—— ——
ASRB
Arithmetic Shift Right
B
INH
371D
—
2
—— ——
ASRD
Arithmetic Shift Right
D
INH
27FD
—
2
—— ——
ASRE
Arithmetic Shift Right
E
INH
277D
—
2
—— ——
ASRM
Arithmetic Shift Right
AM
INH
27BA
—
4
—— —
——
ASRW
Arithmetic Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270D
271D
272D
273D
gggg
gggg
gggg
hh ll
8
—— ——
8
8
8
2
BCC
Branch if Carry Clear
If C = 0, branch
REL8
B4
rr
6, 2 — — — — — — — —
BCLR
Clear Bit(s)
(M) • (Mask) ⇒ M
IND8, X
1708
mm ff
8
—— —— ∆ ∆ 0—
IND8, Y
1718
mm ff
8
IND8, Z
1728
mm ff
8
IND16, X
08 mm gggg
8
IND16, Y
18 mm gggg
8
IND16, Z
28 mm gggg
8
EXT
38 mm hh ll
8
BCLRW Clear Bit(s) in a Word
(M : M + 1) • (Mask) ⇒
M:M+1
IND16, X
IND16, Y
IND16, Z
EXT
2708
2718
2728
2738
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
10 — — — — ∆ ∆ 0 —
10
10
10
BCS²
Branch if Carry Set
If C = 1, branch
REL8
B5
rr
6, 2 — — — — — — — —
BEQ²
Branch if Equal
If Z = 1, branch
REL8
B7
rr
6, 2 — — — — — — — —
BGE^{2 Branch if Greater Than}
If N ⊕ V = 0, branch
REL8
BC
rr
6, 2 — — — — — — — —
or Equal to Zero
BGND
Enter Background
If BDM enabled,
INH
37A6
—
Debug Mode
begin debug;
else, illegal instruction trap
— — — — — ————
BGT^{2 Branch if Greater Than If Z ' (N ⊕ V) = 0, branch}
REL8
BE
rr
6, 2 — — — — — — — —
Zero
BHI²
Branch if Higher
If C ' Z = 0, branch
REL8
B2
rr
6, 2 — — — — — — — —
BITA
Bit Test A
(A) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
—— —— ∆ ∆ 0—
6
6
2
6
6
6
6
6
6
6
M68HC16 Z SERIES
USER’S MANUAL
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
4-15