MC68HC16Z1CAG16 Datasheet, PDF (69/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

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Table 4-1 Addressing Modes
Mode
Accumulator Offset
Extended
Immediate
Indexed 8-Bit
Indexed 16-Bit
Indexed 20-Bit
Inherent
Post-Modified Index
Relative
Mnemonic
E,X
E,Y
E,Z
EXT
EXT20
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
INH
IXP
REL8
REL16
Description
Index register X with accumulator E offset
Index register Y with accumulator E offset
Index register Z with accumulator E offset
Extended
20-bit extended
8-bit immediate
16-bit immediate
Index register X with unsigned 8-bit offset
Index register Y with unsigned 8-bit offset
Index register Z with unsigned 8-bit offset
Index register X with signed 16-bit offset
Index register Y with signed 16-bit offset
Index register Z with signed 16-bit offset
Index register X with signed 20-bit offset
Index register Y with signed 20-bit offset
Index register Z with signed 20-bit offset
Inherent
Signed 8-bit offset added to index register
X after effective address is used
8-bit relative
16-bit relative
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an
operand or an extension field to form a 20-bit effective address.
NOTE
Access across 64-Kbyte address boundaries is transparent. AD-
DR[19:16] of the effective address are changed to make an access
across a bank boundary. Extension field values will not change as a
result of effective address computation.
4.6.1 Immediate Addressing Modes
In the immediate modes, an argument is contained in a byte or word immediately fol-
lowing the instruction. For IMM8 and IMM16 modes, the effective address is the ad-
dress of the argument.
There are three specialized forms of IMM8 addressing.
• The AIS, AIX, AIY, AIZ, ADDD, and ADDE instructions decrease execution time
by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an ap-
propriate register.
• The MAC and RMAC instructions use an 8-bit immediate operand to specify two
signed 4-bit index register offsets.
• The PSHM and PULM instructions use an 8-bit immediate mask operand to indi-
cate which registers must be pushed to or pulled from the stack.
M68HC16 Z SERIES
CENTRAL PROCESSOR UNIT
USER’S MANUAL
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