MC68HC16Z1CAG16 Datasheet, PDF (273/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series users manual

Freescale Semiconductor, Inc.
SYSTEM CLOCK
DIVIDER
512
TO PULSE ACCUMULATOR
EXT.
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
CPR2 CPR1 CPR0
256
128
64
32
16
SELECT
8
4
EXT.
TO CAPTURE/
COMPARE
TIMER
PCLK
PIN
SYNCHRONIZER AND
DIGITAL FILTER
128
64
32
16
SELECT
8
4
2
EXT.
PPR2 PPR1 PPR0
TO
PWM UNIT
Figure 11-2 Prescaler Block Diagram
GPT PRE BLOCK
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler
outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-
vided. Connected to these outputs are two multiplexers, one for the capture/compare
unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]
in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC). After re-
set, the GPT is configured to use system clock divided by four for TCNT and system
clock divided by two for PWMCNT. Initialization software can change the division fac-
tor. The PPR bits can be written at any time, but the CPR bits can only be written once
after reset, unless the GPT is in test or freeze mode.
M68HC16 Z SERIES
USER’S MANUAL
GENERAL-PURPOSE TIMER
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