MC68HC08JB1 Datasheet, PDF (93/216 Pages) Motorola, Inc – Microcontrollers

OSCXCLK
INT
IAB
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 8-16. Stop Mode Entry Timing
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-17. Stop Mode Recovery from Interrupt
8.8 SIM Registers
The SIM has one reset register.
8.8.1 Reset Status Register
This register contains seven flags that show the source of the last reset.
All flag bits are cleared automatically following a read of the register. The
register is initialized on power-up as shown with the POR bit set and all
other bits cleared. However, during a POR or any other internal reset,
the RST pin is pulled low. After the pin is released, it will be sampled 32
XCLK cycles later. If the pin is not above a V_IH at that time, then the PIN
bit in the RSR may be set in addition to whatever other bits are set.
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
93