|
MC68HC08JB1 Datasheet, PDF (61/216 Pages) Motorola, Inc – Microcontrollers | |||
|
◁ |
6.6.2 Stop Mode
The STOP instruction:
⢠Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
⢠Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. The program counter vectors to $FFFCâ$FFFD
($FEFCâ$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC08JB1 â Rev. 2.1
Freescale Semiconductor
Technical Data
61
|
▷ |