MC68HC08JB1 Datasheet, PDF (171/216 Pages) Motorola, Inc – Microcontrollers

11.5.1 Port D Data Register
The port D data register contains a data latch for the PTD0/1 pin.
Address: $0003
Bit 7
6
Read: 0
0
Write:
Reset:
5
4
3
2
0
0
0
0
Unaffected by reset
1
PTD1
Bit 0
PTD0
Additional
Function:
Open-drain Open-drain
25 mA sink 25mA sink
Figure 11-8. Port D Data Register (PTD)
PTD[1:0] — Port D Data Bit-1 and Bit-0
These two read/write bits are software programmable. Data direction
of PTD0/1 pin is under control of these two data bits. Reset has no
effect on port D data. Configure this register so that PTD1 = PTD0.
The infrared LED drive bit, PTDILDD, in the port option control
register (POCR) controls the drive options for the PTD0/1 pin.
(See 11.7 Port Options.)
NOTE:
PTD1 and PTD0 internal pads are bonded together to PTD0/1 pin
forming a 50mA high current drain pin. When both PTD1 and PTD0 are
configured as output, the values of PTD0 and PTD1 should be written
the same.
11.5.2 Data Direction Register D
Data direction register D determines whether PTD0/1 pin is an input or
an output. Writing a logic 1 to DDRD[1:0] bits enable the output buffer for
the PTD0/1 pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
DDRD1
0
0
0
0
0
0
0
Figure 11-9. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
171