MC68HC08JB1 Datasheet, PDF (105/216 Pages) Motorola, Inc – Microcontrollers

The start of a packet (SOP) is signaled by the originating port by driving
the D+ and D– lines from the idle state (also referred to as the J state) to
the opposite logic level (also referred to as the K state). This switch in
levels represents the first bit of the sync field. Figure 9-6 shows the data
signaling and voltage levels for the start of packet and the sync pattern.
V_OH (min.)
V_SE (max)
V_SE (min.)
V_OL (min.)
V_SS
BUS IDLE SOP
FIRST BIT OF PACKET
END OF SYNC
Figure 9-6. SOP, Sync Signaling, and Voltage Levels
9.5.1.2 Packet Identifier Field
The packet identifier field is an 8-bit number comprised of the 4-bit
packet identification and its complement. The field follows the sync
pattern and determines the direction and type of transaction on the bus.
Table 9-2 shows the packet identifier values for the supported packet
types.
Table 9-2. Supported Packet Identifiers
Packet Identifier Value
%1001
%0001
%1101
%0011
%1011
%0010
%1010
%1110
Packet Identifier Type
IN Token
OUT Token
SETUP Token
DATA0 Packet
DATA1 Packet
ACK Handshake
NAK Handshake
STALL Handshake
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
105