MC68HC08JB1 Datasheet, PDF (78/216 Pages) Motorola, Inc – Microcontrollers

Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD
USB
LVI
0
$FE01
Reset Status Register
(RSR)
Write:
POR: 1
0
0
0
0
0
0
0
Read: IF6
IF5
IF4
IF3
IF2
IF1
0
0
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.
FROM CLOCK
DOUBLER
FROM CLOCK
DOUBLER
OSCXCLK
OSCOUT
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 8-3. SIM Clock Signals
8.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
divided by two.
8.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 OSCXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
Technical Data
78
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor