MC68HC08JB1 Datasheet, PDF (84/216 Pages) Motorola, Inc – Microcontrollers

command (refer to Section 9.4 of the Universal Serial Bus Specification
Rev. 1.1) no later than 10ms after the reset is removed.
USB reset can be disabled to generate an internal reset, instead, a USB
interrupt can be generated. (See Section 5. Configuration Register
(CONFIG).)
NOTE: USB reset is disabled when the USB module is disabled by clearing the
USBEN bit of the USB Address Register (UADDR).
8.4.2.7 Registers Values After Different Resets
Some registers are reset by POR or LVI reset only. Table 8-3 shows the
registers or register bits which are unaffected by normal resets.
Table 8-3. Registers not Affected by Normal Reset
Bits
URSTD, LVIDIS
USBEN
PULLEN
All
All
All
All
All
DDRA7
Registers
CONFIG
UADDR
UCR3
USR0, USR1
UE0D0–UE0D7
UE1D0–UE1D7
UE2D0–UE2D7
PTA, PTC, PTD, and PTE
DDRA
After Reset
(except POR or LVI)
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
After POR or LVI
0
0
0
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
0
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescalar for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of OSCXCLK.
Technical Data
84
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor