MC68HC08JB1 Datasheet, PDF (91/216 Pages) Motorola, Inc – Microcontrollers

A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset. If the COP disable bit, COPD,
in the mask option register is logic 0, then the computer operating
properly module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 8-13. Wait Mode Entry Timing
Figure 8-14 and Figure 8-15 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 8-14. Wait Recovery from Interrupt
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
91