MC68HC08JB1 Datasheet, PDF (118/216 Pages) Motorola, Inc – Microcontrollers

TXD1IE — Endpoint 1 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 1 to generate CPU
interrupt requests when the TXD1F bit becomes set. Reset clears the
TXD1IE bit.
1 = Transmit endpoints 1 can generate a CPU interrupt request
0 = Transmit endpoints 1 cannot generate a CPU interrupt request
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 0 to generate CPU
interrupt requests when the TXD0F bit becomes set. Reset clears the
TXD0IE bit.
1 = Transmit endpoint 0 can generate a CPU interrupt request
0 = Transmit endpoint 0 cannot generate a CPU interrupt request
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the receive endpoint 0 to generate CPU
interrupt requests when the RXD0F bit becomes set. Reset clears the
RXD0IE bit.
1 = Receive endpoint 0 can generate a CPU interrupt request
0 = Receive endpoint 0 cannot generate a CPU interrupt request
9.8.3 USB Interrupt Register 1
Address: $003A
Bit 7
6
5
4
3
2
1
Read: EOPF RSTF TXD2F
0
TXD1F RESUMF TXD0F
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 9-17. USB Interrupt Register 1 (UIR1)
Bit 0
RXD0F
0
EOPF — End-of-Packet Detect Flag
This read-only bit is set when a valid end-of-packet sequence is
detected on the D+ and D– lines. Software must clear this flag by
writing a logic 1 to the EOPFR bit.
Reset clears this bit. Writing to EOPF has no effect.
1 = End-of-packet sequence has been detected
0 = End-of-packet sequence has not been detected
Technical Data
118
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor