MC68HC08JB1 Datasheet, PDF (50/216 Pages) Motorola, Inc – Microcontrollers

5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. Bit-5 and
bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared
during any reset. Since the various options affect the operation of the
MCU, it is recommended that this register be written immediately after
reset. The configuration register is located at $001F. The configuration
register may be read at any time.
Address: $001F
Bit 7
Read: 0
Write:
6
5
4
3
2
1
0
URSTD LVID SSREC COPRS STOP
Reset: 0
0
0*
0*
0
0
0
= Unimplemented
* URSTD and LVID bits are reset by POR or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
Bit 0
COPD
0
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU.
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI circuit
1 = Disable LVI circuit
0 = Enable LVI circuit
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
2048×OSCXCLK cycles instead of a 4096×OSCXCLK cycle delay.
1 = Stop mode recovery after 2048×OSCXCLK cycles
0 = Stop mode recovery after 4096×OSCXCLK cycles
Technical Data
50
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor