MC68HC08JB1 Datasheet, PDF (164/216 Pages) Motorola, Inc – Microcontrollers

NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_REG
or V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
Register Name
Bit 7
$0000
Read:
Port A Data Register
(PTA)
Write:
Reset:
PTA7
$0002
Read: 0
Port C Data Register
(PTC)
Write:
Reset:
$0003
Read: 0
Port D Data Register
(PTD)
Write:
Reset:
Read:
$0004
Data Direction Register A
(DDRA)
Write:
Reset:
DDRA7
0*
* DDRA7 bit is reset by POR or LVI reset only.
Read: 0
$0006
Data Direction Register C
(DDRC)
Write:
Reset: 0
Read: 0
$0007
Data Direction Register D
(DDRD)
Write:
Reset: 0
$0008
Read: 0
Port E Data Register
(PTE)
Write:
Reset:
Read: 0
$0009
Data Direction Register E
(DDRE)
Write:
Reset: 0
$001D
Port Option Control ^Read:
Register Write:
(POCR) _Reset:
PTE20P
0
6
PTA6
5
PTA5
0
0
0
0
DDRA6 DDRA5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTDILDD
0
0
= Unimplemented
4
3
PTA4 PTA3
Unaffected by reset
0
0
Unaffected by reset
0
0
Unaffected by reset
DDRA4 DDRA3
0
0
0
0
0
0
0
0
0
0
PTE4 PTE3
Unaffected by reset
DDRE4 DDRE3
0
0
PTE4P PTE3P
0
0
2
PTA2
0
0
DDRA2
0
0
0
0
0
0
0
0
PCP
0
1
PTA1
0
PTD1
DDRA1
0
0
0
DDRD1
0
PTE1
DDRE1
0
0
0
Bit 0
PTA0
PTC0
PTD0
DDRA0
0
DDRC0
0
DDRD0
0
0
0
0
PAP
0
Figure 11-1. I/O Port Register Summary
Technical Data
164
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor