MC68HC08JB1 Datasheet, PDF (76/216 Pages) Motorola, Inc – Microcontrollers

8.7.1
8.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.8.1 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2 Introduction
This section describes the system integration module (SIM), which
supports up to 8 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. The SIM is a system state
controller that coordinates CPU and exception timing. A block diagram
of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM
I/O registers. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Technical Data
76
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor