MC68HC08JB1 Datasheet, PDF (203/216 Pages) Motorola, Inc – Microcontrollers

Technical Data — MC68HC08JB1
Section 15. Low Voltage Inhibit (LVI)
15.1 Contents
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
15.4 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .204
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
15.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the V_DD pin and generates a reset when the V_DD
voltage falls to the LVI trip (V_LVR) voltage.
15.3 Functional Description
Figure 15-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V_DD voltage.
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V_DD drops to below the set trip point.
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
203