MC68HC08JB1 Datasheet, PDF (126/216 Pages) Motorola, Inc – Microcontrollers

9.8.8 USB Control Register 3
Address: $001A
Bit 7
6
5
4
3
2
1
Bit 0
Read: TX1ST
0
0
OSTALL0 ISTALL0
PULLEN ENABLE2 ENABLE1
Write:
TX1STR
Reset: 0
0
0
0
0
0*
0
0
= Unimplemented
* PULLEN bit is reset by POR or LVI reset only.
Figure 9-22. USB Control Register 3 (UCR3)
TX1ST — Endpoint 0 Transmit First Flag
This read-only bit is set if the endpoint 0 data transmit flag (TXD0F) is
set when the USB control logic is setting the endpoint 0 data receive
flag (RXD0F). In other words, if an unserviced endpoint 0 transmit flag
is still set at the end of an endpoint 0 reception, then this bit will be set.
This bit lets the firmware know that the endpoint 0 transmission
happened before the endpoint 0 reception.
Reset clears this bit.
1 = IN transaction occurred before SETUP/OUT
0 = IN transaction occurred after SETUP/OUT
TX1STR — Clear Endpoint 0 Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set.
Writing a logic 0 to the TX1STR has no effect. Reset clears this bit.
OSTALL0 — Endpoint 0 Force STALL Bit for OUT token
This read/write bit causes endpoint 0 to return a STALL handshake
when polled by an OUT token by the USB host controller. The USB
hardware clears this bit when a SETUP token is received. Reset
clears this bit.
1 = Send STALL handshake
0 = Default
Technical Data
126
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor