MC68HC08JB1 Datasheet, PDF (201/216 Pages) Motorola, Inc – Microcontrollers

14.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Reset:
Clear COP counter
Unaffected by reset
Figure 14-3. COP Control Register (COPCTL)
14.6 Interrupts
The COP does not generate CPU interrupt requests.
14.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
14.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
14.7.2 Stop Mode
Stop mode turns off the OSCXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
201