MC68HC08JB1 Datasheet, PDF (204/216 Pages) Motorola, Inc – Microcontrollers

V_DD
LVID
LOW V_DD
DETECTOR
V_DD > V_LVR = 0
V_DD < V_LVR = 1
LVI RESET
Figure 15-1. LVI Module Block Diagram
15.4 LVI Control Register (CONFIG)
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
URSTD LVID SSREC COPRS STOP COPD
Reset: 0
0
0
0
0
0
0
0
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
= Unimplemented
Figure 15-2. Configuration Register (CONFIG)
LVID —þLow Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
15.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
15.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
15.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
Technical Data
204
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor