MC68HC08JB1 Datasheet, PDF (199/216 Pages) Motorola, Inc – Microcontrollers

NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the reset status register (RSR).
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
14.4 I/O Signals
The following paragraphs describe the signals shown in Figure 14-1.
14.4.1 OSCXCLK
OSCXCLK is the clock doubler output signal. OSCXCLK frequency is
double of the crystal frequency.
14.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
14.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 14.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
14.4.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the COP prescaler
4096 OSCXCLK cycles after power-up.
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
199