MC68HC08JB1 Datasheet, PDF (174/216 Pages) Motorola, Inc – Microcontrollers

The PTE1 pullup enable bit, PTE20P, in the port option control
register (POCR) enables pullup on PTE1, regardless of the pin is
configured as an input or an output. (See 11.7 Port Options.)
PTE4 pin functions as an external interrupt when PTE4IE=1 in the
IRQ option control register (IOCR) and USBEN=0 in the USB address
register (USB disabled). (See 12.9 IRQ Option Control Register.)
D– and D+ — USB Data Pins
D– and D+ are the differential data lines used by the USB module.
(See Section 9. Universal Serial Bus Module (USB).)
The USB module enable bit, USBEN, in the USB address register
(UADDR) controls the pin options for PTE4/D– and PTE3/D+. When
the USB module is enabled, PTE4/D– and PTE3/D+ function as USB
data pins D– and D+. When the USB module is disabled, PTE4/D–
and PTE3/D+ function as 10mA open-drain pins for PS/2 clock and
data use.
The Pullup enable bit, PULLEN, in the USB control register 3 (UCR3)
enables a 1.5kΩ pullup on D– pin when the USB module is enabled.
(See 9.8.8 USB Control Register 3.)
NOTE:
PTE4/D– pin has two programmable pullup resistors. One is used for
PTE4 when the USB module is disabled and another is used for D–
when the USB module is enabled.
TCH0 — Timer Channel 0 I/O Bits
The PTE1/TCH0 pin is the TIM input capture/output compare pin. The
edge/level select bits, ELS0B and ELS0A, determine whether the
PTE1/TCH0 pin is timer channel I/O pin or general-purpose I/O pin.
(See Section 10. Timer Interface Module (TIM).)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins.
Technical Data
174
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor