MC68HC08JB1 Datasheet, PDF (172/216 Pages) Motorola, Inc – Microcontrollers

DDRD[1:0] — Data Direction Register D Bit-1 and Bit-0
These two read/write bits control PTD0/1 pin data direction. Reset
clears DDRD[1:0], configuring PTD0/1 pin as an input.
Configure this register so that DDRD1 = DDRD0.
1 = PTD0/1 pin configured as output
0 = PTD0/1 pin configured as input
PTD0/1 pin is open-drain when configured as output.
NOTE:
Avoid glitches on PTD0/1 pin by writing to PTD[1:0] before changing
DDRD[1:0] bits from 0 to 1.
Figure 11-10 shows the port D I/O circuit logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRD1/DDRD0
PTD1/PTD0
PTD0/1
Technical Data
172
READ PTD ($0003)
Figure 11-10. Port D I/O Circuit
When bit DDRD[1:0] is a logic 1, reading address $0003 reads the
PTD0/1 data latch. When bit DDRD[1:0] is a logic 0, reading address
$0003 reads the voltage level on the pin. The data latch can always be
written, regardless of the state of its data direction bit. Table 11-4
summarizes the operation of the port D pins.
Table 11-4. Port D Pin Functions
DDRD
Bit
0
1
PTD Bit
PTD[1:0]
PTD[1:0]
I/O Pin Mode
Accesses
to DDRD
Read/Write
Input, Hi-Z^{(1) DDRD[1:0]}
Output
DDRD[1:0]
NOTES:
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Accesses to PTD
Read
Pin
PTD0/1
Write
PTD[1:0]⁽²⁾
PTD[1:0]
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor