MC68HC08JB1 Datasheet, PDF (119/216 Pages) Motorola, Inc – Microcontrollers

RSTF — USB Reset Flag
This read-only bit is set when a valid reset signal state is detected on
the D+ and D– lines. If the URSTD bit of the configuration register
(CONFIG) is clear, this reset detection will generate an internal reset
signal to reset the CPU and other peripherals including the USB
module. If the URSTD bit is set, this reset detection will generate an
USB interrupt. This bit is cleared by writing a logic 1 to the RSTFR bit.
This bit also is cleared by a POR reset.
NOTE: The USB bit in the RSR register (see 8.8.1 Reset Status Register) is
also a USB reset indicator.
TXD2F — Endpoint 2 Data Transmit Flag
This read-only bit is set after the data stored in endpoint 2 transmit
buffers has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD2FR bit.
To enable the next data packet transmission, TX2E also must be set.
If the TXD2F bit is not cleared, a NAK handshake will be returned in
the next IN transaction.
Reset clears this bit. Writing to TXD2F has no effect.
1 = Transmit on endpoint 2 has occurred
0 = Transmit on endpoint 2 has not occurred
TXD1F — Endpoint 1 Data Transmit Flag
This read-only bit is set after the data stored in the endpoint 1 transmit
buffer has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD1FR bit. To
enable the next data packet transmission, TX1E also must be set. If
the TXD1F bit is not cleared, a NAK handshake will be returned in the
next IN transaction.
Reset clears this bit. Writing to TXD1F has no effect.
1 = Transmit on endpoint 1has occurred
0 = Transmit on endpoint 1has not occurred
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor
Technical Data
119