MC68HC08JB1 Datasheet, PDF (82/216 Pages) Motorola, Inc – Microcontrollers

• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
OSC1
PORRST
OSCXCLK
OSCOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
Figure 8-7. POR Recovery
8.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 2¹² – 2⁴ OSCXCLK cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
V_DD + V_HI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise.
Technical Data
82
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor