MC68HC08JB1 Datasheet, PDF (156/216 Pages) Motorola, Inc – Microcontrollers

10.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
TCNTH Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
TCNTL Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
Technical Data
156
MC68HC08JB1 — Rev. 2.1
Freescale Semiconductor