MC9S08QG8 Datasheet, PDF (82/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 6 Parallel Input/Output Control
6.4.4 Port B Control Registers
The pins associated with port B are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the port B pins independent of the parallel I/O register.
6.4.4.1 Port B Internal Pullup Enable (PTBPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTBPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
R
W
Reset:
7
PTBPE7
0
6
PTBPE6
5
PTBPE5
4
PTBPE4
3
PTBPE3
2
PTBPE2
1
PTBPE1
0
0
0
0
0
0
Figure 6-12. Internal Pullup Enable for Port B Register (PTBPE)
Table 6-8. PTBPE Register Field Descriptions
0
PTBPE0
0
Field
Description
7:0
PTBPE[7:0]
Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
6.4.4.2 Port B Slew Rate Enable (PTBSE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTBSEn). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins which are configured as input.
R
W
Reset:
7
PTBSE7
1
6
PTBSE6
5
PTBSE5
4
PTBSE4
3
PTBSE3
2
PTBSE2
1
PTBSE1
1
1
1
1
1
1
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)
Table 6-9. PTBSE Register Field Descriptions
0
PTBSE0
1
Field
Description
7:0
PTBSE[7:0]
Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
82
Freescale Semiconductor