MC9S08QG8 Datasheet, PDF (271/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Appendix A Electrical Characteristics
A.8.3 SPI Timing
Table A-10 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-10. SPI Timing
No.
Function
Operating frequency
Master
Slave
1 SPSCK period
Master
Slave
2 Enable lead time
Master
Slave
3 Enable lag time
Master
Slave
4 Clock (SPSCK) high or low time
Master
Slave
5 Data setup time (inputs)
Master
Slave
6 Data hold time (inputs)
Master
Slave
7 Slave access time
8 Slave MISO disable time
9 Data valid (after SPSCK edge)
Master
Slave
10 Data hold time (outputs)
Master
Slave
11 Rise time
Input
Output
12 Fall time
Input
Output
Symbol
f_op
t_SPSCK
t_Lead
t_Lag
t_WSPSCK
t_SU
t_HI
t_a
t_dis
t_v
t_HO
t_RI
t_RO
t_FI
t_FO
Min
Max
f_Bus/2048
0
2
4
1/2
1
1/2
1
t_cyc – 30
t_cyc – 30
15
15
0
25
—
—
—
—
0
0
—
—
—
—
f_Bus/2
f_Bus/4
2048
—
—
—
—
—
1024 t_cyc
—
—
—
—
—
1
1
25
25
—
—
t_cyc – 25
25
t_cyc – 25
25
Unit
Hz
t_cyc
t_cyc
t_SPSCK
t_cyc
t_SPSCK
t_cyc
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
271