MC9S08QG8 Datasheet, PDF (260/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Appendix A Electrical Characteristics
A.4 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-3. ESD and Latch-up Test Conditions
Model
Description
Human
Body
Series resistance
Storage capacitance
Number of pulses per pin
Machine _{Series resistance}
Storage capacitance
Number of pulses per pin
Latch-up Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
—
R1
C
—
Value
1500
100
3
0
200
3
– 2.5
7.5
Unit
Ω
pF
Ω
pF
V
V
Table A-4. ESD and Latch-Up Protection Characteristics
No.
Rating¹
Symbol
Min
Max Unit
1
Human body model (HBM)
V_HBM
± 2000
—
V
2
Machine model (MM)
V_MM
± 200
—
V
3
Charge device model (CDM)
V_CDM
± 500
—
V
4
Latch-up current at T_A = 85°C
I_LAT
± 100
—
mA
1 _{Parameter is achieved by design characterization on a small sample size from typical devices}
under typical conditions unless otherwise noted.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
260
Freescale Semiconductor