MC9S08QG8 Datasheet, PDF (233/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Timer/PWM (S08TPMV2)
7
6
5
4
3
2
1
0
R Bit 7
6
5
4
3
2
1
Bit 0
W
Any write to TPMCNTL clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure 16-5. Timer Counter Register Low (TPMCNTL)
When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.
16.3.3 Timer Counter Modulo Registers (TPMMODH:TPMMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMMODH or TPMMODL inhibits TOF and overflow interrupts until the other byte is written. Reset
sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 16-6. Timer Counter Modulo Register High (TPMMODH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 16-7. Timer Counter Modulo Register Low (TPMMODL)
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
233