MC9S08QG8 Datasheet, PDF (243/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 17
Development Support
17.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins. Debug is done
through commands fed into the target MCU via the single-wire background debug interface. The debug
module provides a means to selectively trigger and capture bus information so an external development
system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external
access to the address and data signals.
17.1.1 Module Configuration
The alternate BDC clock source is the ICSLCLK. This clock source is selected by clearing the CLKSW
bit in the BDCSCR register. For details on ICSLCLK, see Section 10.4, “Functional Description” of the
ICS chapter.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
243