MC9S08QG8 Datasheet, PDF (158/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 11 Inter-Integrated Circuit (S08IICV1)
Clear
IICIF
Y
Master
N
Mode
?
TX
Tx/Rx
RX
?
Last Byte
Transmitted
Y
?
N
RXAK=0
?
N
Y
Last
Byte to Be Read _Y
?
N
End of
Y _{Addr Cycle}
(Master Rx)
?
N
Write Next
Byte to IICD
Y
2nd Last
Byte to Be Read
?
N
Set NACK =1
Generate
Stop Signal
(MST = 0)
Switch to
Rx Mode
Y Arbitration
Lost
?
N
Clear ARBL
N
Y
(Read)
IAAS=1
?
Y
IAAS=1
?
Y
N
Address Transfer
Data Transfer
SRW=1
?
N ^(Write)
TX/RX
RX
?
TX
Set TX
Mode
Write Data
to IBDR
Y ACK from
Receiver
?
N
Tx Next
Byte
Read Data
from IICD
and Store
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
(MST = 0)
Read Data
from IICD
and Store
Dummy Read
from IICD
Dummy Read
from IICD
RTI
Figure 11-3. Typical IIC Interrupt Routine
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
158
Freescale Semiconductor